1. Technological Field
The present invention relates to integrated circuits and, more particularly, to systems and methods for power reduction through dynamic adjustment of memory rail voltage.
2. Background
The increased use of mobile, battery-powered devices has increased the importance of reducing power consumption in large heterogeneous integrated circuits (ICs), such as system-on-a-chip (SoC) and the memory storage devices onboard the SoC, such as Static Random Access Memory (SRAM). Included among the techniques to achieve power reductions, is dynamically adjusting supply voltages based on tracking processes, temperature, and voltage drop.
However, in large ICs with many millions of transistors on a single die, there are several supply domains that can have independent voltage levels. Additionally, an IC can have a number of heterogeneous devices, for example, transistors with different threshold voltages (Vth) and channel lengths, with each type of device having its own performance and power attributes. Dynamically adjusting supply voltages for a whole IC can also be very difficult due to the use of (1) different technology library implementations such as high-speed and high-density; (2) different supply domains with different configurations of voltage regulators (e.g., using a switching mode power supply (SMPS) or low drop-out (LDO) regulator); and (3) a variety of hard macros that can each have a different supply domain and independent power controls.